This invention relates to an event based test system for testing semiconductor devices, and more particularly, to an event based test system having a modular architecture for simultaneously testing a plurality of semiconductor devices including memory and logic devices. The event based test system detects functional faults as well as physical faults in embedded memories and stand-alone memories.
Semiconductor memories are considered to be the most vital microelectronic component of digital logic system design, such as computers and microprocessor based applications. In particular, embedded memories are the key components in the present day ICs. These embedded memories implement register files, FIFOs, data-cache, instruction-cache, transmit/receive buffers, storage for texture processing etc. At the present time, both embedded memories and stand-alone memory devices are tested by the cycle based test patterns generated by LSI tester""s ALPG (algorithmic pattern generator) unit. It appears there is no method available today to test memory devices using event-based vectors. The present invention is directed to a method to conduct memory testing in the event environment. This method is applicable to both stand-alone memories and embedded memories.
In an event based test system, notions of events are employed, which are any changes of the logic state in signals to be used for testing a semiconductor device. For example, such changes are rising and falling edges of test signals or timing edges of strobe signals. The timings of the events are defined with respect to a time length from a reference time point. Typically, such a reference time point is a timing of the previous event (delta time). Alternatively, such a reference time point is a fixed start time common to all of the events (absolute time).
In an event based test system, since the timing data in a timing memory (event memory) does not need to include complicated information regarding waveform, vector, delay and etc. at each and every test cycle, the description of the timing data can be dramatically simplified. In the event based test system, as noted above, typically, the timing (event) data for each event stored in an event memory is expressed by a time difference between the current event and the last event. Since such a time difference between the adjacent events (delta time) is small, unlike a time difference from a fixed start point (absolute time), a size of the data in the memory can also be small, resulting in the reduction of the memory capacity.
During the IC design, designers create RTL (register transfer level) models of the memory devices such as embedded memories. These models are written in a high-level description language (HDL), such as Verilog or VHDL. Using these models, designers develop Verilog/VHDL simulation testbenches. The basic method in these simulation testbenches is to perform cycle by cycle memory read/write operations to ensure that data transaction to and from the memory is valid. These are known as functional testbenches. The test vectors in a functional testbench are in the event form and they can be used to perform functional testing using an event based test system as described in the U.S. patent application Ser. No. 09/340,371 and U.S. patent application Ser. No. 09/406,300 owned by the same assignee of this invention.
These functional test vectors detect functional errors in terms of the validity of data transaction to and from the memory under test. These test vectors are not developed to detect physical failures (such as memory cell stuck-at faults, coupling between two cells, bridging between lines, pattern sensitive fault, etc), and hence do not detect physical faults in the memories. In the presence of such faults, the data transaction to and from the memory under test may remain valid but the data itself can be erroneous. Hence, the testing of physical faults is required.
Secondly, if the functional testing of the memory is done on an event based test system such as described in the U.S. patent applications noted above, then it is also natural and cost-effective to test the memory in the event environment. Hence, a method is needed to generate memory test vectors in the event format and then to apply these event formed vectors to the memory.
Therefore, it is an object of the present invention to provide an event based semiconductor test system for generating memory test vectors in the event format for testing memory devices such as embedded memories and/or stand-alone memories.
It is another object of the present invention to provide an event based test system for detecting functional faults as well as physical faults in the memory device under test by generating memory test vectors in the event format with use of an algorithmic test pattern in the cycle format.
It is a further object of the present invention to provide an event based test system having a modular architecture for performing two or more different tests in parallel, at one of which is a memory test.
It is a further object of the present invention to provide an event based test system having a modular architecture in which two or more tester modules (pin-unit groups) operate independently from one another for performing two or more different or identical memory tests in parallel at the same time.
The event based test system of the present invention is comprised of two or more tester modules each having a plurality of pin units where each pin unit corresponds to a pin of a semiconductor device under test (DUT), a main frame for accommodating two or more tester modules, a test fixture provided on the main frame for electrically connecting between the tester modules and the DUT, a host computer for controlling an overall operation of the test system by communicating with the tester modules, and a data storage accessible by the host computer for storing a library of algorithmic patterns and software routines for producing memory test patterns for testing memories embedded in the DUT or stand-alone memories. In the present invention, each of the tester modules operates independently from one another, and memory test algorithm and information regarding the memories to be tested are specified in the host computer prior to the memory testing.
According to the present invention, the event based test system is capable of producing the memory test vectors in the event format for testing memory devices. Such memory test vectors can be produced with use of algorithmic patterns in the cycle based format. Thus, not only functional faults, but also physical faults of the memory devices under test can be detected. Since the event based test system has a modular architecture in which two or more tester modules operate independently from one another, two or more different or identical memory tests or two or more different types of test can be performed simultaneously. Both stand-alone and embedded memories can be tested in the event environment that is the same as the design simulation environment. The present invention also allows the use of any memory test algorithm to detect physical faults of the memory. By generating the memory vectors in the event form off-line, test productivity can also be improved considerably.